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functional block diagram ain bpo/upo encode ref in acom dcom latches correction logic range select x4 coarse 4-bit flash 8-bit ladder matrix fine 4-bit flash ad671 3 4 4 8 12 20 dac otr msb bit1-12 dav 21 16 19 23 22 24 17 18 3-bit flash 3 dac 3-bit flash 14 13 15 12 1 v cc v logic ee v rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a monolithic 12-bit 2 mhz a/d converter ad671 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features 12-bit resolution 24-pin skinny dip package conversion time: 500 ns maxad671j/k/s-500 conversion time: 750 ns maxad671j/k/s-750 low power: 475 mw unipolar (0 v to +5 v, 0 v to +10 v) and bipolar input ranges ( 6 5 v) twos complement or offset binary output data out-of-range indicator mil-std-883 compliant versions available product description the ad671 is a high speed monolithic 12-bit a/d converter offering conversion rates of up to 2 mhz (500 ns conversion time). the combination of a merged high speed bipolar/cmos process and a novel architecture results in a combination of speed and power consumption far superior to previously avail- able hybrid implementations. additionally, the greater reliability of monolithic construction offers improved system reliability and lower costs than hybrid designs. the ad671 uses a subranging flash conversion technique, with digital error correction for possible errors introduced in the first part of the conversion cycle. an on-chip timing generator pro- vides strobe pulses for each of the four internal flash cycles and assures adequate settling time for the interflash residue ampli- fier. a single encode pulse is used to control the converter. the performance of the ad671 is made possible by using high speed, low noise bipolar circuitry in the linear sections and low power cmos for the logic sections. analog devices abcmos-1 process provides both high speed bipolar and 2-micron cmos devices on a single chip. laser trimmed thin-film resistors are used to provide accuracy and temperature stability. the ad671 is available in two conversion speeds and perfor- mance grades. the ad671j and k grades are specified for op- eration over the 0 c to +70 c temperature range. the ad671s grades are specified for operation over the C55 c to +125 c temperature range. all grades are available in a 0.300 inch wide 24-pin ceramic dip. the j and k grades are also available in a 24-pin plastic dip. product highlights 1. the ad671 offers a single chip 2 mhz analog-to-digital conversion function in a space saving 24-pin dip. 2. input signal ranges are 0 v to +5 v and 0 v to +10 v unipo- lar, and C5 v to +5 v bipolar, selected by pin strapping. in- put resistance is 1.5 k w . power supplies are +5 v and C5 v, and typical power consumption is less than 500 mw. 3. the external +5 v reference can be chosen to suit the dc ac- curacy and temperature drift requirements of the application. 4. output data is available in unipolar, bipolar offset or bipolar twos complement binary format. 5. an out of range output bit indicates when the input signal is beyond the ad671s input range. 6. the ad671 is available in versions compliant with the mil- std-883. refer to the analog devices military products databook or current ad671/883b data sheet for detailed specifications. obsolete
ad671Cspecifications dc specifications (t min to t max with v cc = +5 v 6 5%, v logic = +5 v 6 10%, v ee = C5 v 6 5%, v ref = +5.000 v, unless otherwise noted) ad671j/s-500 ad671k-500 parameter min typ max min typ max units resolution 12 12 bits accuracy (+25 c) integral nonlinearity (inl) t min to t max 6 4 6 2 lsb differential nonlinearity (dnl) t min to t max 10 11 bits no missing codes 10 bits guaranteed 11 bits guaranteed unipolar offset l 6 4 6 4 lsb bipolar zero l 6 10 6 10 lsb gain error 2 0.1 0.25 0.1 0.25 % fsr temperature coefficients 3 unipolar offset 6 10 6 10 ppm/ c bipolar zero 6 15 6 15 ppm/ c gain error 6 20 6 20 ppm/ c analog input input ranges bipolar C5 +5 C5 +5 volts unipolar 0+50+5 volts 0 +10 0 +10 volts input resistance 10 volt range 1.0 1.5 2.0 1.0 1.5 2.0 k w 5 volt range 0.5 0.75 1.0 0.5 0.75 1.0 k w input capacitance 10 10 pf reference input resistance 2.4 3.5 4.7 2.4 3.5 4.7 k w power supplies power supply rejection 4 v cc (+5 v 0.25 v) 6 1 6 1 lsb v logic (+5 v 0.5 v) 6 1 6 1 lsb v ee (C5 v 0.25 v) 6 1 6 1 lsb operating voltages v cc +4.75 +5.25 +4.75 +5.25 volts v logic +4.5 +5.5 +4.5 +5.5 volts v ee C5.25 C4.75 C5.25 C4.75 volts operating current i cc 46 56 46 56 ma i logic 5 3 6 3 6 ma i ee 46 56 46 56 ma power consumption 475 621 475 621 mw temperature range specified (j/k) 0 +70 0 +70 c specified (s) C55 +125 c notes 1 adjustable to zero with external potentiometers. see offset/gain calibration section for additional information. 2 full-scale range (fsr) is 5 v for the 0 v to 5 v range and 10 v for the 0 v to 10 v and C5 v to +5 v ranges. 3 25 c to t min and 25 c to t max . 4 change in gain error as a function of the dc supply voltage. 5 tested under static conditions. see figure 12 for typical curves of i logic vs. conversion rate and output loading. specifications subject to change without notice. specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25 c and +70 c. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested. rev. b C2C obsolete
ad671j/s-750 ad671k-750 parameter min typ max min typ max units resolution 12 12 bits accuracy (+25 c) integral nonlinearity (inl) t min to t max (j) 6 2 6 1.5 lsb t min to t max (s) 6 2.5 lsb differential nonlinearity (dnl) t min to t max 11 12 bits no missing codes 11 bits guaranteed 12 bits guaranteed unipolar offset l 6 4 6 4 lsb bipolar zero l 6 10 6 10 lsb gain error 2 0.1 0.25 0.1 0.25 % fsr temperature coefficients 3 unipolar offset 6 10 6 10 ppm/ c bipolar zero 6 15 6 15 ppm/ c gain error 6 20 6 20 ppm/ c analog input input ranges bipolar C5 +5 C5 +5 volts unipolar 0+50+5 volts 0 +10 0 +10 volts input resistance 10 volt range 1.0 1.5 2.0 1.0 1.5 2.0 k w 5 volt range 0.5 0.75 1.0 0.5 0.75 1.0 k w input capacitance 10 10 pf reference input resistance 2.4 3.5 4.7 2.4 3.5 4.7 k w power supplies power supply rejection 4 v cc (+5 v 0.25 v) 6 1 6 1 lsb v logic (+5 v 0.5 v) 6 1 6 1 lsb v ee (C5 v 0.25 v) 6 1 6 1 lsb operating voltages vcc +4.75 +5.25 +4.75 +5.25 volts v logic +4.5 +5.5 +4.5 +5.5 volts v ee C5.25 C4.75 C5.25 C4.75 volts operating current i cc 46 56 46 56 ma i logic 5 3 6 3 6 ma i ee 46 56 46 56 ma power consumption 475 621 475 621 mw temperature range specified (j/k) 0 +70 0 +70 c specified (s) C55 +125 c notes 1 adjustable to zero with external potentiometers. see offset/gain calibration section for additional information. 2 full-scale range (fsr) is 5 v for the 0 v to 5 v range and 10 v for the 0 v to 10 v and C5 v to +5 v ranges. 3 25 c to t min and 25 c to t max . 4 change in gain error as a function of the dc supply voltage. 5 tested under static conditions. see figure 12 for typical curves of i logic vs. conversion rate and output loading. specifications subject to change without notice. specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25 c and +70 c. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested. ad671 dc specifications (t min to t max with v cc = +5 v 6 5%, v logic = +5 v 6 10%, v ee = C5 v 6 5%, v ref = +5.000 v, unless otherwise noted) rev. b C3C obsolete
ad671Cspecifications digital specifications (for all grades t min to t max , with v cc = +5 v 6 5%, v logic = +5 v 6 10%, v ee = C5 v 6 5%, v ref = +5.000 v, unless otherwise noted) rev. b C4C parameter symbol min typ max units logic input high level input voltage v ih +2.0 v low level input voltage v il +0.8 v high level input current (v in = v logic )i ih C10 +10 m a low level input current (v in = 0 v) i il C10 +10 m a input capacitance c in 5pf logic outputs high level output voltage (i oh = 0.5 ma) v oh +2.4 v low level output voltage (i ol = 1.6 ma) v ol +0.4 v output capacitance c out 5pf specifications shown in boldface are tested on all devices at final electrical test. results from those tests are used to calculate outgoing quality levels. all min and max specifications are guaranteed, although only those shown in boldface are tested. specifications subject to change without notice. switching specifications parameter symbol min typ max units conversion time (ad671-500) t c 475 500 ns (ad671-750) t c 725 750 ns encode pulse width high (ad671-500) t enc 20 30 ns (ad671-750) t enc 20 50 ns encode pulse width low t encl 20 ns dav pulse width (ad671-500) t dav 75 200 ns (ad671-750) t dav 75 300 ns encode falling edge delay t f 0ns start new conversion delay t r 0ns data and otr delay from dav falling edge t dd 1 20 75 ns data and otr valid before dav rising edge t ss 2 20 75 ns notes 1 t dd is measured from when the falling edge of dav crosses 0.8 v to when the output crosses 0.4 v or 2.4 v with a 25 pf load capacitor on each output pin. 2 t ss is measured from when the outputs cross 0.4 v or 2.4 v to when the rising edge of dav crosses 2.4 v with a 25 pf load capacitor on each output pin. (for all grades t min to t max with v cc = +5 v 6 5%, v logic = +5 v 6 10%, v ee = C5 v 6 5%, v il = 0.8 v, v ih = 2.0 v, v ol = 0.4 v and v oh = 2.4 v) figure 1. ad671 timing diagrams a. encode pulse high b. encode pulse low obsolete
ad671 rev. b C5C ordering guide temperature package model l linearity range options 2 ad671jd-500 4 lsb 0 c to +70 c d-24a ad671kd-500 2 lsb 0 c to +70 c d-24a ad671jd-750 2 lsb 0 c to +70 c d-24a ad671kd-750 1.5 lsb 0 c to +70 c d-24a ad671sd-500 4 lsb C55 c to +125 c d-24a ad671sd-750 2.5 lsb C55 c to +125 c d-24a notes 1 for details on grade and package offerings screened in accordance with mil-std-883, refer to the analog devices military products databook or current ad671/883 data sheet. 2 d = ceramic dip. absolute maximum ratings* with respect parameter to min max units v cc acom C0.5 +6.5 volts v ee acom C6.5 +0.5 volts v logic dcom C0.5 +6.5 volts acom dcom C1.0 +1.0 volts v cc v logic C6.5 +6.5 volts encode dcom C0.5 v logic +0.5 volts ref in acom C0.5 v cc +0.5 volts ain, bpo/upo acom C6.5 11.0 volts junction temperature +175 c storage temperature C65 +150 c lead temperature (10 sec) +300 c power dissipation 1000 mw *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad671 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. obsolete
ad671 rev. b C6C ad671 pin description symbol pin type name and function acom 22 p analog ground. ain 20 ai analog input signal. bit1 (msb) 12 do most significant bit. bit2Cbit11 11C2 do data bits 2C11. bit12 (lsb) 1 do least significant bit. bpo/upo 21 ai bipolar or unipolar configuration pin. connect to ain for 0 v to +5 v span, to acom for 0 v to +10 v span and to ref in for C5 v to +5 v span. dav 15 do data available output. the rising edge of dav indicates an end of conversion and can be used to latch current data into an external register. the falling edge of dav can be used to latch previous data into an external register. dcom 18 p digital ground. encode 16 di the ad671 starts a conversion on the rising edge of the encode pulse. msb 13 do inverted most significant bit. provides twos complement output data format. otr 14 do out of range is active high when the analog input is beyond the input range of the converter. ref in 19 ai +5 v reference input. v cc 23 p +5 v analog power. v ee 24 p C5 v analog power. v logic 17 p +5 v digital power. type: ai = analog input di = digital input do = digital output p = power connection diagram pinout 1 2 3 4 5 6 7 8 9 10 11 24 23 22 21 20 19 18 17 16 15 14 12 13 top view (not to scale) ad671 bit12 (lsb) bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 (msb) msb otr dav encode dcom ref in ain bpo/upo acom v cc v ee v logic obsolete
ad671 rev. b C7C definitions of specifications integral nonlinearity (inl) integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. the point used as zero occurs 1/2 lsb (1.22 mv for a 10 v span) before the first code transition (all zeros to only the lsb on). full scale is defined as a level 1 1/2 lsb beyond the last code transition (to all ones). the deviation is measured from the low side transition of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus every code must have a finite width. guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes represented by bits 1C10 must be present over all operating ranges. guaranteed no missing codes to 11- or 12-bit resolution indicates that all 2048 and 4096 codes, respectively, must be present over all op- erating ranges. unipolar offset the first transition should occur at a level 1/2 lsb above analog common. unipolar offset is defined as the deviation of the ac- tual from that point. this offset can be adjusted as discussed later. the unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustments. bipolar zero in the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1/2 lsb below analog common. the bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature. gain error the last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 1 1/2 lsb below the nominal full scale (9.9963 volts for 10.000 volts full scale). the gain er- ror is the deviation of the actual level at the last transition from the ideal level. the gain error can be adjusted to zero as shown in figures 7, 8 and 9. temperature coefficients the temperature coefficients for unipolar offset, bipolar zero and gain error specify the maximum change from the initial (+25 c) value to the value at t min or t max . power supply rejection the only effect of power supply error on the performance of the device will be a small change in gain. the specifications show the maximum full-scale change from the initial value with the supplies at the various limits. signal-to-noise and distortion (s/n+d) ratio s/n+d is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components, including har- monics but excluding dc. the value for s/n+d is expressed in decibels. effective number of bits (enob) enob is calculated from the expression snr = 6.02n + 1.8 db, where n is equal to the effective number of bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is ex- pressed as a percentage or in decibels. peak spurious or peak harmonic component the peak spurious or peak harmonic component is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full- scale input signal. theory of operation the ad671 uses a successive subranging architecture. the ana- log to digital conversion takes place in four independent steps or flashes. the analog input signal is subranged to an intermediate residue voltage for the final 12-bit result by utilizing multiple flashes with subtraction dacs (see the ad671 functional block diagram). the ad671 can be configured to operate with unipolar (0 v to +5 v, 0 v to +10 v) or bipolar ( 5 v) inputs by connecting ain (pin 20), refin (pin 19) and bpo/upo (pin 21) as shown in figure 2. the ad671 conversion cycle begins by simply providing an ac- tive high pulse on the encode pin (pin 16). the rising edge of the encode pulse starts the conversion. the falling edge of the encode pulse is specified to operate within a win- dow of time: less than 30 ns after the rising edge of encode (ad671-500) and less than 50 ns after the falling edge of encode (ad671C750) or after the falling edge of dav. the time window prevents digitally coupled noise from being intro- duced during the final stages of conversion. an internal timing generator circuit accurately controls all internal timing. ain bpo/upo ref in 20 21 19 ain acom bpo/upo ref in 20 22 21 19 ain bpo/upo ref in 20 21 19 ain ain ain 0 to 10v + 5v ref + 0 to 5v + 5v ref + 5v to 5v ? 5v ref + figure 2. input range connections obsolete
ad671 rev. b C8C upon receipt of an encode command, the first 3-bit flash converts the analog input voltage. the 3-bit result is passed to a correction logic register and a segmented current output dac. the dac output is connected through a resistor (within the range/span select block) to ain. a residue voltage is created by subtracting the dac output from ain, which is less than one eighth of the full-scale analog input. the second flash has an input range that is configured with one bit of overlap with the previous dac. the overlap allows for errors during the flash conversion. the first residue voltage is connected to the second 3-bit flash and to the noninverting input of a high speed, differ- ential, gain-of-four amplifier. the second flash result is passed to the correction logic register and to the second segmented cur- rent output dac. the output of the second dac is connected to the inverting input of the differential amplifier. the differen- tial amplifier output is connected to a two step backend 8-bit flash. this 8-bit flash consists of coarse and fine flash convert- ers. the result of the coarse 4-bit flash converter, also config- ured to overlap one bit of dac 2, is connected to the correction logic register and selects one of 16 resistors from which the fine 4-bit flash will establish its span voltage. the fine 4-bit flash is connected directly to the output latches. the ad671 will flag an out-of-range condition when the input voltage exceeds the analog input range. otr (pin 14) is active high when an out of range high or low condition exists. bits 1C12 are high when the analog input voltage is greater than the selected input range and low when the analog input is less than the selected input range. applying the ad671 driving the ad671 analog input the ad671 uses a very high speed current output dac to sub- tract a known voltage from the analog input. this results in very fast steps of current at the analog input. it is important to recog- nize that the signal source driving the analog input of the ad671 must be capable of maintaining the input voltage under dynamically-changing load conditions. when the ad671 starts its conversion cycle, the subtraction dac will sink up to 5 ma (see figure 3) from the source driving the analog input. the source must respond to this current step by settling the input voltage back to a fraction of an lsb before the ad671 makes its final 12-bit decision. a/d dac ad671 iin idac r ia/d + figure 3. driving the analog input unlike successive approximation a/ds, where the input voltage must settle to a fraction of a 12-bit lsb before each successive bit decision is made, the ad671 requires the analog input volt- age settle to within 12 bits before the third flash conversion, approximately 200 ns. this free 200 ns is useful in applica- tions requiring a sample-and-hold amplifier (sha), overlapping the shas hold mode settling time within the 200 ns window will increase total system throughput. see the discrete sample- and-hold section for a high speed sha application. input buffer amplifier the closed-loop output impedance of an op amp is equal to the open loop output impedance (usually a few hundred ohms) di- vided by the loop gain at the frequency of interest. it is often assumed that loop gain of a follower-connected op amp is suffi- ciently high to reduce the closed-loop output impedance to a negligibly small value, particularly if the input signal is low frequency. at higher frequencies the open-loop gain is lower, increasing the output impedance which decreases the instanta- neous analog input voltage and produces an error. the recommended wideband, fast settling input amplifiers for use with the ad671 are the ad841, ad843, ad845 or the ad847. the ad841 is unity gain stable and recommended as a follower connected op amp. the ad843 and ad845 fet in- puts make them ideal for high speed sample-and-hold amplifiers and the ad847 can be used as a low power, high speed buffer. figure 4 shows the ad841 driving the ad671. as shown in the figure the analog input voltage should be produced with respect to the acom pin. ad841 ain ref in bpo/upo acom + bit1 bit12 dcom ad671 encode dav otr msb 10 11 4 5 6 20 23 24 17 22 18 19 21 13 14 15 16 v cc v ee v logic 5v ref + 5v 1 12 figure 4. input buffer amplifier reference input the ad671 uses a standard +5 volt reference. the initial accu- racy and temperature stability of the reference can be selected to meet specific system requirements. like the analog input, fast switching input-dependent currents are modulated at the refer- ence input pin (ref inCpin 19). however, unlike the analog input the reference input is held at a constant +5 volts with the use of capacitor. the recommended reference is the ad586, a +5 v precision reference with an output buffer amplifier. fig- ure 5 shows the ad671 configured in the 5 v input range. the 6.8 m f capacitor maintains a constant +5 volts under the dynamically changing load conditions. an optional 1 m f noise reduction capacitor can be connected to the ad586, further re- ducing broadband output noise. to minimize ground voltage drops the ad586s ground pin should be tied as close as pos- sible to the ad671s acom pin. see figures 20, 21 and 22 for pcb layout recommendations. obsolete
ad671 rev. b C9C ain ref in bpo/upo acom bit1 bit12 dcom ad671 encode dav otr msb 20 23 24 17 22 18 19 21 13 14 15 16 v cc v ee v logic 5v 6 4 8 15v + 2 1 m f +v in v out noise reduction gnd 1 12 ad586 u3 c14 6.8 m f c15 u4 figure 5. ad586 as reference input for ad671 grounding and decoupling rules proper grounding and decoupling should be a primary design objective in any high speed, high resolution system. the ad671 separates analog and digital grounds to optimize the manage- ment of analog and digital ground currents in a system. the ad671 is designed to minimize the current flowing from acom (pin 22) by directing the majority of the current from v cc (+5 vCpin 23) to v ee (C5 vCpin 24). minimizing analog ground currents hence reduces the potential for large ground voltage drops. this can be especially true in systems that do not utilize ground planes or wide ground runs. acom is also con- figured to be code independent, therefore reducing input depen- dent analog ground voltage drops and errors. the input current supplied by the external reference (refinCpin 19) and the ma- jority of the full-scale input signal (ainCpin 20) are also di- rected to v e . also critical in any high speed digital design are the use of proper digital grounding techniques to avoid potential cmos ground bounce. figure 6 is provided to assist in the proper layout, grounding and decoupling techniques. table i is a list of grounding and decoupling guidelines that should be reviewed before laying out a printed circuit board. ain ref in bpo/upo acom bit1 bit12 dcom ad671 encode dav otr msb 20 23 24 17 22 18 19 21 13 14 15 16 v cc v ee v logic 5v 1 12 v in + + 5v ref *ground plane recommended 0.1 m f 10 m f 10 m f10 m f 0.1 m f 0.1 m f + 5v + 5v 5v agp* dgp* figure 6. ad671 grounding and decoupling table i. grounding and decoupling guidelines power supply decoupling comment capacitor values 0.1 m f (ceramic) and 10 m f (tantalum). (surface mount chip capacitors recom- mended to reduce lead inductance). capacitor locations directly at positive and negative supply pins to respective ground plane. grounding analog ground ground plane or wide ground return connected to the analog power supply. digital ground ground plane or wide ground return connected to the digital power supply. analog and digital ground connected together once at the ad671. unipolar (0 v to +10 v) calibration the ad671 is factory trimmed to minimize offset, gain and lin- earity errors. in some applications the offset and gain errors of the ad671 need to be externally adjusted to zero. this is ac- complished by trimming the voltage at bpo/upo (pin 21) and refin (pin 19). in those applications the ad588, a high preci- sion pin programmable voltage reference, is an ideal choice. the ad588 includes a reference cell and three additional amplifiers which can be configured to provide offset and gain trims for the ad671. the circuit in figure 7 is recommended for calibrating offset and gain errors of the ad671 when configured in the 0 v to +10 v input range. ain ref in bpo/upo acom bit1 bit12 dcom ad671 encode dav otr msb 20 23 24 17 22 18 19 21 13 14 15 16 v cc v ee v logic 1 12 0.1 m f 10 m f 10 m f10 m f 0.1 m f 0.1 m f + 5v + 5v 5v 0 to 10v + 10 m f 0.1 m f 10 m f 1 14 15 50 1 m f 150 13 12 11 8 10 9 5 7 6 4 3 5k r2 100k 50 1 m f ad588 0.1 m f 150pf 10k 39k 15v + 2 16 + 15 15 r1 100 figure 7. unipolar (0 v to +10 v) calibration the ad671 is intended to have a nominal 1/2 lsb offset so that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the codes above it and below it). thus, the first transition ( from 0000 0000 0000 to 0000 0000 0001) will oc cur for an input level of +1/2 lsb (1.22 mv for 10 v range). if the offset trim resistor r2 is used, obsolete
ad671 rev. b C10C it should be trimmed as above, although a different offset can be set for a particular system requirement. this circuit will give ap- proximately 50 mv of offset trim range. the gain trim is done by applying a signal 1 1/2 lsbs below the nominal full scale (9.9963 for a 10 v range). trim r1 to give the last transition (1111 1111 1110 to 11111111 1111). unipolar (0 v to +5 v) calibration the connections for the 0 v to +5 v input range calibration is shown in figure 8. the ad586, a +5 v precision voltage refer- ence, is an excellent choice for this mode of operation because of its performance, stability and optional fine trim. the ad845 (16 mhz, low power, low cost op amp) is used to maintain the +5 volts under the dynamically changing load conditions of the reference input. ad845 ain refin bpo/upo acom bit1 bit12 dcom ad671 encode dav otr msb 6 7 2 3 4 20 23 24 17 22 18 19 21 13 14 15 16 v cc v ee v logic 1 12 ad845 6 7 2 3 4 6 5 4 8 2 +v in + 15v v out trim gnd noise reduction ad586 1 m f 8 1 +15v 0.1 m f 390 +15v ?5v 0.1 m f 0 to +5v ?5v 0.1 m f +15v 0.1 m f 10k w 1k w figure 8. unipolar (0 v to +5 v) calibration the ad671 offset error must be trimmed within the analog in- put path, either directly in front of the ad671 or within the sig- nal conditioning chain, eliminating offset errors induced by the signal conditioning circuitry. figure 8 shows an example of how the offset error can be trimmed in front of the ad671. the ad586 is configured in the optional fine trim mode to provide +6%/C2% (+240 lsbs/C80 lsbs) of gain trim. the procedure for trimming the offset and gain errors is similar to that used for the unipolar 10 v range with the analog input values set to one- half the 10 v range values. bipolar ( 6 5 v) calibration the connections for the bipolar input range is shown in figure 9. the ad588 is configured to provide dual +5 v outputs. pro- viding a +5 v reference voltage for the ad671 gain trim and the +5 v bpo/upo input for the bipolar offset trim. ain ref in bpo/upo acom bit1 bit12 dcom ad671 encode dav otr msb 20 23 24 17 22 18 19 21 13 14 15 16 v cc v ee v logic 1 12 5v 0.1 m f 10 m f 0.1 m f 10 m f 1 14 15 50 150pf 50 13 12 11 8 10 9 5 7 6 4 3 1 m f ad588 150pf r2 100 39k 15v + 2 16 + 15 15 r1 100 6.2k w figure 9. bipolar ( 5 v) calibration bipolar calibration is similar to unipolar calibration. first, a sig- nal 1/2 lsb above negative full scale (C4.9988 v) is applied and r1 is trimmed to give the first transition (0000 0000 0000 to 0000 0000 0001). then a signal 1 1/2 lsb below positive full scale (+4.9963) is applied, and r2 is trimmed to give the last transition (1111 1111 1110 to 1111 1111 1111). output latches figure 10 shows the ad671 connected to the 74hc574 octal d-type edge triggered latches with 3-state outputs. the latch can drive highly capacitive loads (i.e., bus lines, i/o ports) while maintaining the data signal integrity. the maximum set-up and hold times of the 574 type latch must be less than 20 ns (t dd and t ss minimum). to satisfy the requirements of the 574 type latch the recommended logic families are hc, s, as, als, f or bct. new data from the ad671 is latched on the rising edge of the dav (pin 24) output pulse. previous data can be latched by inverting the dav output with a 7404 type inverter. see fig- ures 20, 21 and 22 for pcb layout recommendations. 1d 2d 3d 4d 5d 6d 7d 8d clk 1q 2q 3q 4q 5q 6q 7q 8q 1d 2d 3d 4d 5d 6d 7d 8d clk 1q 2q 3q 4q 5q 6q 7q 8q bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 bit9 bit10 bit11 bit12 dav data bus 3-state control ad671 oc oc 74hc574 74hc574 u6 u5 figure 10. ad671 to output latches out of range an out of range condition exists when the analog input voltage is beyond the input range (0 v to +5 v, 0 v to +10 v, 5 v) of the converter. otr (pin 14) is set low when the analog input voltage is within the analog input range. otr is set high and will remain high when the analog input voltage exceeds the input range by typically 1/2 lsb (otr transition is tested to 6 lsbs of accuracy) from the center of the full-scale output codes. otr will remain high until the analog input is within the input range and another conversion is completed. by logical anding otr with the msb and its complement overrange high or underrange low conditions can be detected. table ii is a truth table for the over/under range circuit in figure 11. sys- tems requiring programmable gain conditioning prior to the ad671 can immediately detect an out of range condition, thus eliminating gain selection iterations. table ii. out of range truth table otr msb analog input is 0 0 in range 0 1 in range 1 0 underrange 1 1 overrange obsolete
ad671 rev. b C11C msb otr msb over = "1" under = "1" figure 11. overrange or underrange logic output data format the ad671 provides both msb and msb outputs, delivering data in positive true straight binary for unipolar input ranges and positive true offset binary or twos complement for bipolar input ranges. straight binary coding is used for systems that ac- cept positive-only signals. if straight binary coding is used with bipolar input signals a 0 v input would result in a binary output of 2048. the application software would have to subtract 2048 to determine the true input voltage. most processors typically perform math on signed integers and assume data is in that for- mat. twos complement format minimizes software overhead which is especially important in high speed data transfers, such as a dma operation. the cpu is not bogged down performing data conversion steps, hence increasing the total system throughput. table iii. output data format input analog digital range coding input 1 output otr 2 0 to +5 v straight binary C0.00061 v 0000 0000 0000 1 0 v 0000 0000 0000 0 +5 v 1111 1111 1111 0 >+5.00061 v 1111 1111 1111 1 0 to +10 v straight binary C0.00122 v 0000 0000 0000 1 0 v 0000 0000 0000 0 +10 v 1111 1111 1111 0 3 +10.00122 v 1111 1111 1111 1 C5 v to +5 v offset binary C5.00122 v 0000 0000 0000 1 C5 v 0000 0000 0000 0 0 v 1000 0000 0000 0 +4.99756 v 1111 1111 1111 0 3 +4.99878 v 1111 1111 1111 1 C5 v to +5 v 2s complement C5.00122 v 1000 0000 0000 1 (using msb ) C5 v 1000 0000 0000 0 0 v 0000 0000 0000 0 +4.99756 v 0111 1111 1111 0 3 +4.99878 v 0111 1111 1111 1 notes 1 voltages listed are with offset and gain errors adjusted to zero. 2 typical performance. 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1k 10k 100k 1m 10m conversion rate ?hz ma cl = 0pf cl = 30pf cl = 50pf figure 12. i logic vs. conversion rate for various capacitive loads on the digital outputs i logic vs. conversion rate figure 12 shows the typical logic supply current vs. conversion rate for various capacitive loads on the digital outputs. obsolete
ad671 rev. b C12C high performance sample-and-hold amplifier (sha) in order to take full advantage of the ad671s high speed capa- bilities, a sample-and-hold amplifier (sha) with fast acquisition capabilities and rigid accuracy requirements is essential. one possibility is a hybrid sha such as the htc-0300a, but often a cost effective alternative like the one shown in figure 13 may be a better solution. this discrete sha requires very few compo- nents and is able to acquire signals to 0.01% accuracy in less than 350 nanoseconds. combined with the ad671, signals with bandw idths up to 500 khz can be converted with 12-bit accu racy. sd5001 in1 in2 in3 in4 out1 out2 out3 out4 g1 g2 g3 g4 u8 ad841 u9 ad845 s/h s/h r6 r7 r8 250 r9 r10 10k r11 250 u10 c24 c25 c26 c27 c28 20pf c29 20pf d1 1n4148 vr2 100k r13 r14 226 c34 5pf 1k 10 11 4 6 5 15v + 0.1 m f 2k 15v 0.1 m f 4 5 13 12 3 6 14 11 2 1 8 16 9 15v 1k 2 3 4 15v 7 1k 6 0.1 m f 0.1 m f 15v + in v (5vp?) adj pedestal figure 13. d iscrete high speed sample-and-hold amplifier circuit description the discrete sha shown in figure 13 is a closed-loop, nonin- verting architecture which accepts 5 v p-p inputs. the overall gain of the sha is +2 in order to accommodate the 10 v input span of the ad671. the ad841, with a 0.01% settling time of 110 ns, is the suggested input buffer to the sha. the circuit also employs a sd5001 which contains four ultrahigh speed dmos switches (q1Cq4). the high cmrr, low input offset current, and fast settling time of the ad845 op amp are all criti- cal features necessary for optimal performance of the discrete sha. in sample mode, q1 and q3 of the sd5001 are closed (q2 and q4 are open). c28 is charged to the input voltage level at a rate primarily determined by the time constant, r9 ? c28. simulta- neously, c29 is connected to ground through a 250 ohm resis- tor. if c28 is equal to c29, charge injection from q1 will be approximately equal to charge injection from q3 based on the symmetry of the circuit and the inherent matching of the switch capacitances. the resultant pedestal errors appear as a common- mode signal to the ad845. vr2, r13, r14, and c34 may be in- cluded if further reduction of pedestal e rror is required. in hold mode, q2 and q4 are closed (q1 and q3 are open) to reduce feedthrough. the input signal is attenuated C78 db relative to the input signal at frequencies up to 500 khz. the ad845 buffers the voltage on c28 and also provides the wide- band, low-impedance output necessary to drive the input of the ad671. droop, which occurs as a result of leakage currents, will appear on c28 and will similarly appear on c29. like pedestal errors, droop appears as a common-mode signal to the ad845 and is greatly reduced by the differential nature of the circuit. voltage droop is typically 5 m v/ m s. cross coupled latch as noted in the theory of operation, the encode pulse is specified to operate within a window of time. the circuit in fig- ure 14 can be used to generate a valid encode pulse if a clock pulse width of greater than 30 ns is available. ad671 encode dav 1/4 7402 1/4 7402 1/4 7402 t w figure 14. cross coupled latch timing description figure 15 shows the timing requirements for the discrete sha. the complementary s/h inputs are hcmos-compatible al- though larger gate voltages will improve performance by lower- ing the on resistances of the dmos switches. it should be noted that a conversion is started before the sha has settled to 0.01% accuracy. the discrete sha takes advantage of the fact that the ad671 does not require a 12-bit accurate input until it is 150 ns into its conversion cycle. see figures 21, 22 and 23 for pcb layout recommendations. dav s/h t sample = 1 m s t conversion = 500ns t acquire ? 350ns t settle 350ns encode figure 15. ad671 to discrete sha timing diagram dynamic performance in most sampling applications the dynamic performance of the system is limited by the performance of the sha. the shas dynamic performance can be selected to meet the system sam- pling requirements. figures 16 and 17 are typical fft plots using the discrete sha in figure 13. figure 16. typical fft plot of ad671 and discrete sha f in = 100 khz obsolete
ad671 rev. b C13C figure 17. typical fft plot of ad671 and discrete sha f in = 500 khz dynamic characteristics (@ +25 c, tested using the discrete sha in figure 15 with v cc = +5 v, v logic = +5 v, v ee = C5 v, f sample = 1 msps) 1 model ad671jd-500 typ units effective number of bits (enob) f in = 100 khz 11.3 bits f in = 490 khz 11.2 bits signal-to-noise and distortion (s/n+d) ratio f in = 100 khz 70 db f in = 490 khz 68 db total harmonic distortion (thd) f in = 100 khz C80 db f in = 490 khz C75 db peak spurious (dc to 490 khz) C79 db peak harmonic component (dc to 490 khz) C76 db note 1 f in amplitude = C0.2 db @ 100 khz and C0.9 db @ 490 khz, bipolar mode unless otherwise indicated. see definition of specifications for additional information. multichannnel data acquisition system the ad684, a quad high speed sample-and-hold amplifier is ideally suited for multichannel data acquisition applications. figure 18 shows a typical data acquisition circuit using the ad684 (sha), adg201hs (multiplexer), ad588 (reference) and the ad671. the ad684 is configured to simultaneously sample four analog inputs. each held analog input voltage can be selected by the multiplexer and buffered by the ad841. the ad671 is connected in the bipolar input range ( 5 v). figure 18. data acquisition system using the ad684 and the ad671 obsolete
ad671 rev. b C14C ad671 to adsp-2100a interface figure 19 demonstrates the ad671 to adsp-2100a interface. the 2100a with a clock frequency of 12.5 mhz can execute an instruction in one 80 ns cycle. the ad671 is configured to per- form continuous time sampling. the dav output of the ad671 is asserted at the end of each conversion. dav can be used to latch the conversion result into the two 574 octal d-latches. the falling edge of the sampling clock is used to generate an inter- rupt (irq3) for the processor. upon interrupt, the adsp- 2100a starts a data memory read by providing an address on the dma bus. the decoded address generates oe for the latches and the processor reads their output over the dma bus. the conversion result is read within a single processor cycle. ad671 to adsp-2101/adsp-2102 interface figure 20 is identical to the 2100a interface except the sam- pling clock is used to generate an interrupt (irq2) for the pro- cessor. upon interrupt the adsp-2101a starts a data memory read by providing an address on the address (a) bus. the de- code address generates oe for the d-latches and the processor reads their output over the data (d) bus. reading the conver- sion result is thus completed within a single processor cycle. adsp-2100a dma0:13 dma0:15 dmack address bus decode + 5v q0:7 d0:7 574 oe q0:7 d0:7 574 oe data bus d0:3 dav bit1:12 sampling clock encode 16 8 4 8 8 4 dmrd irq3 ad671 figure 19. ad671 to adsp-2100a interface adsp-2101 a0:13 d0:15 address bus decode q0:7 d0:7 574 oe q0:7 d0:7 574 oe data bus d0:3 dav bit1:12 sampling clock encode 16 8 4 8 8 4 rd irq2 ad671 figure 20. ad671 to adsp-2101/adsp-2102 interface figure 21. pcb silkscreen and component placement diagram for figures 5, 10 and 13 obsolete
ad671 rev. b C15C figure 22. pcb solder side layout for figures 5, 10 and 13 figure 23. pcb component side layout for figures 5, 10 and 13 obsolete
ad671 rev. b C16C c1426aC10C9/91 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 24-pin plastic dip (suffix n) 24-pin ceramic dip (suffix d) pin 1 0.295 6 0.01 (7.49 6 0.26) 1 0.175 (4.45) 0.018 6 0.002 (0.46 6 0.05) typ 1.200 6 0.012 (30.48 6 0.31) 0.05 (1.27) typ seating plane 0.100 6 0.005 (2.54 6 0.13) 0.300 6 0.010 (7.49 6 0.25) 0.010 + 0.002 ?.001 ( 0.025 + 0.05 ) ?.03 0.085 6 0.009 (2.16 6 0.23) 1.100 6 0.005 (27.94 6 0.13) toll non accum notes 1. lead no. 1 identified by dot or notch. 2. ceramic dip leads will be either gold or tin plated in accordance with mil-m-385 to requirements. obsolete

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